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lt4256-1/lt4256-2 1 425612fa applicatio s u features typical applicatio u descriptio u the lt ? 4256-1/lt4256-2 are high voltage hot swap tm controllers that allow a board to be safely inserted and removed from a live backplane. an internal driver drives an external n-channel mosfet switch to control supply voltages ranging from 10.8v to 80v. the lt4256-1/lt4256-2 features an adjustable analog foldback current limit. if the supply remains in current limit for more than a programmable time, the n-channel mosfet shuts off and the pwrgd output asserts low. the lt4256-2 automatically restarts after a time-out delay. the lt4256-1 latches off until the uv pin is cycled low. the pwrgd output indicates when the output voltage rises above a programmed level. an external resistor string from v cc provides programmable undervoltage protection. the lt4256 can be used as an upgrade to lt1641 designs. see table 1 on page 14 for upgraded specifications. the lt4256-1 and lt4256-2 are available in an 8-pin so package that is pin compatible with the lt1641. hot board insertion electronic circuit breaker/power bussing industrial high side switch/circuit breaker 24v/48v industrial/alarm systems ideally suited for 12v, 24v and 48v distributed power systems 48v telecom systems , ltc and lt are registered trademarks of linear technology corporation. allows safe board insertion and removal from a live backplane controls supply voltage from 10.8v to 80v foldback current limiting overcurrent fault detection drives an external n-channel mosfet programmable supply voltage power-up rate undervoltage protection latch off operation mode (lt4256-1) automatic retry (lt4256-2) available in an 8-pin so package positive high voltage hot swap controllers hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 4256 ta01 0.02 ? lt4256-1/ lt4256-2 sense 6 2 3 4 87 1 5 v cc gate fb pwrgd uv timer gnd v in 48v gnd (short pin) irf530 cmpz5241b 11v 8.06k 64.9k 100 ? 4.02k 10 ? 36.5k pwrgd v out 48v 2a 27k c l 33nf 0.1 f 10nf smat70a uv = 36v pwrgd = 40v 48v, 2a hot swap controller pwrgd 50v/div v out 50v/div inrush current 500ma/div v in 50v/div 2.5ms/div 4256 ta02 lt4256 start-up behavior c l = 225 f
lt4256-1/lt4256-2 2 425612fa order options tape and reel: add #tr lead free: add #pbf lead free tape and reel: add #trpbf lead free part marking: http://www.linear.com/leadfree/ (note 1) supply voltage (v cc ) ................................ C 0.3 to 100v sense, pwrgd ....................................... C 0.3 to 100v gate (note 2) ................................ C 0.3v to v cc + 10v maximum input current (gate) ......................... 200 a fb, uv ........................................................ C 0.3 to 44v timer ..................................................... C 0.3v to 4.3v maximum input current (timer) ....................... 100 a operating temperature lt4256c ................................................. 0 c to 70 c lt4256i ............................................. C 40 c to 85 c storage temperature range ................ C 65 c to 150 c lead temperature (soldering, 10 sec)................. 300 c absolute axi u rati gs w ww u consult ltc marketing for parts specified with wider operating temperature ranges. package/order i for atio uu w order part number s8 part marking 42561 42561i 42562 42562i lt4256-1cs8 lt4256-1is8 lt4256-2cs8 lt4256-2is8 t jmax = 125 c, ja = 110 c/w electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 48v unless otherwise noted. symbol parameter conditions min typ max units v cc operating voltage 10.8 80 v i cc operating current 1.8 3.9 ma v uvlh undervoltage threshold v cc low-to-high transition 3.96 4 4.04 v v uvhys hysteresis 0.25 0.4 0.55 v i inuv uv input current uv 1.2v C0.1 C1 a uv = 0v C1.5 C3 a v uvrth fault latch reset threshold voltage 0.4 0.85 1.2 v v sensetrip sense pin trip voltage (v cc C v sense ) fb = 0v 5.5 14 22 mv fb 2v 45 55 65 mv i insns sense pin input current v sense = v cc 40 70 a i pu gate pull-up current charge pump on, ? v gate = 7v C16 C32 C63 a i pd gate pull-down current any fault, v gate = 3v 40 62 80 ma ? v gate external n-channel gate drive (note 2) v gate C v cc , 10.8v v cc 20v 4.5 8.8 12.5 v 20v v cc 80v 10 11.6 12.8 v v fb fb voltage threshold fb high-to-low transition 3.95 3.99 4.03 v fb low-to-high transition 4.2 4.45 4.65 v v fbhys fb hysteresis voltage 0.3 0.45 0.6 v v olpgd pwrgd output low voltage i o = 1.6ma 0.25 0.4 v i o = 5ma 0.6 1 v i pwrgd pwrgd pin leakage current v pwrgd = 80v 0.1 1 a i infb fb input current fb = 4.5v C0.1 C 1 a i timerpu timer pull-up current timer = 3v, during fault C 63 C 105 C147 a i timerpd timer pull-down current timer = 3v 1.5 3 5 a v thtimer timer shut-down threshold c timer = 10nf 4.3 4.65 5 v d timer duty cycle (retry mode) 1.5 3 4.5 % 1 2 3 4 8 7 6 5 top view v cc sense gate timer uv fb pwrgd gnd s8 package 8-lead plastic so
lt4256-1/lt4256-2 3 425612fa t phluv uv low to gate low 1.7 3 s t plhuv uv high to gate high c gate = 0 6 9 s t phlfb fb low to pwrgd low 0.8 2 s t plhfb fb high to pwrgd high 3.2 5 s t phlsense (v cc C v sense ) high to gate low v cc C v sense = 275mv 1 3 s electrical characteristics the denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. v cc = 48v unless otherwise noted. symbol parameter conditions min typ max units note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: an internal clamp limits the gate pin to a minimum of 10v above v cc . driving this pin to a voltage beyond the clamp voltage may damage the part. typical perfor a ce characteristics uw i cc vs temperature pwrgd thresholds vs temperature pwrgd output voltage vs i pwrgd i cc vs v cc uv thresholds vs temperature sense pin regulation voltage vs temperature temperature ( c) C50 3.5 3.6 uv thresholds (v) 3.7 3.8 3.9 4.1 C25 02550 4256 g01 75 100 4.0 h-l threshold l-h threshold temperature ( c) 10 sense pin regulation voltage (mv) 15 20 48 58 4256 g02 53 fb = 0v fb > 2v C50 C25 0 255075100 v cc (v) 10 2.0 2.5 3.5 40 60 4256 g03 1.5 1.0 20 30 50 70 80 0.5 0 3.0 i cc (ma) temperature ( c) 0 i cc (ma) 0.5 1.0 1.5 2.5 4256 g04 2.0 v cc = 48v C50 C25 0 255075100 temperature ( c) 3.9 4.0 pwrgd thresholds (v) 4.1 4.2 4.3 4.5 4256 g05 4.4 h-l threshold l-h threshold C50 C25 0 255075100 i pwrgd (ma) 0 0 v pwrgd (v) 1 2 3 4 6 2 468 4256 g06 10 12 5 specifications are at t a = 25 c unless otherwise noted.
lt4256-1/lt4256-2 4 425612fa typical perfor a ce characteristics uw gate pin pull-up current vs temperature gate pin pull-down current vs temperature uv pin current vs uv pin voltage v gate ?v cc voltage vs temperature timer pin currents vs temperature v gate ?v cc voltage vs temperature timer pin currents vs v cc timer shutdown threshold vs temperature temperature ( c) C40 gate pin pull-up current ( a) C35 C30 C20 0 4256 g07 C10 C25 C5 C15 C50 C25 0 255075100 temperature ( c) 56 gate pin pull-down current (ma) 57 58 60 63 4256 g08 62 59 61 C50 C25 0 255075100 v uv (v) 0 C1.4 i uv ( a) C1.2 C0.8 C0.6 C0.4 20 30 40 0.4 4256 g09 C1.0 12 4 350 C0.2 0 0.2 temperature ( c) 0 v gate C v cc voltage (v) 6 8 4 2 14 12 4256 g10 10 v cc = 10.8v v cc = 12v v cc = 18v C50 C25 0 25 50 75 100 temperature ( c) 10.0 v gate C v cc voltage (v) 10.5 11.0 12.0 14.0 4256 g11 13.0 13.5 11.5 12.5 v cc = 80v v cc = 48v v cc = 20v C50 C25 0 25 50 75 100 v cc (v) 10 i timer ( a) 0 2.5 5.0 40 60 4256 g13 C80 C100 20 30 50 70 80 C120 C140 pull-up current pull-down current temperature ( c) 0 timer shutdown threshold (v) 4.2 4.4 4.8 5.4 4256 g14 5.2 4.6 5.0 C50 C25 0 25 50 75 100 specifications are at t a = 25 c unless otherwise noted. temperature ( c) C50 C140 i timer ( a) C120 C100 C80 0 10 C25 02550 4256 g12 75 100 5 pull-down current pull-up current
lt4256-1/lt4256-2 5 425612fa typical perfor a ce characteristics uw fb pin current vs fb pin voltage gate pull-down capability vs v cc below minimum operating voltage v fb (v) 0 C0.4 i fb ( a) C0.3 C0.2 C0.1 0 0.1 0.2 10 20 30 40 4256 g15 50 v cc (v) 0 0 i gate (ma ) 10 20 30 40 60 2 468 4256 g16 10 12 50 specifications are at t a = 25 c unless otherwise noted.
lt4256-1/lt4256-2 6 425612fa pi fu ctio s uuu uv (pin 1): undervoltage sense. uv is an input that enables the output voltage. when uv is driven above 4v, gate will start charging and the output turns on. when uv goes below 3.6v, gate discharges and the output shuts off. pulsing uv low for a minimum of 5 s after a current limit fault cycle resets the fault latch (lt4256-1) and allows the part to turn back on. this command is only accepted after timer has discharged below 0.65v. to disable uv sens- ing, connect uv to a voltage beween 5v and 44v. fb (pin 2): power good comparator input. fb monitors the output voltage through an external resistive divider. when the voltage on fb is lower than the high-to-low threshold of 3.99v, pwrgd is pulled low and released when fb is pulled above the 4.45v low-to-high threshold. the voltage present on fb affects foldback current limit (see figure 7 and related discussion). pwrgd (pin 3): power good output. pwrgd is pulled low whenever the voltage on fb falls below the 3.99v high- to-low threshold voltage. it goes into a high impedance state when the voltage on fb exceeds the low-to-high threshold voltage. an external pull-up resistor can pull pwrgd to a voltage higher or lower than v cc . gnd (pin 4): device ground. this pin must be tied to a ground plane for best performance. timer (pin 5): timing input. an external timing capacitor from timer to gnd programs the maximum time the part is allowed to remain in current limit. when the part goes into current limit, a 105 a pull-up current source starts to charge the timing capacitor. when the voltage on timer reaches 4.65v (typ), gate pulls low; the timer pull-up current will be turned off and the capacitor is discharged by a 3 a pull-down current. when timer falls below 0.65v (typ), gate turns on again for the lt4256-2. uv must be cycled low after timer has discharged below 0.65v (typ) to reset the lt4256-1. if uv is not cycled low (lt4256-1), gate remains latched off and timer is discharged to near gnd. under an output short-circuit condition, the lt4256-2 cycles on and off with a 3% duty cycle. gate (pin 6): high side gate drive for the external n- channel mosfet. an internal charge pump guarantees at least 10v of gate drive for v cc supply voltages above 20v and 4.5v of gate drive for v cc supply voltages between 10.8v and 20v. the rising slope of the voltage on gate is set by an external capacitor connected from gate to gnd and an internal 32 a pull-up current source from the charge pump output. if the current limit is reached, the gate voltage is adjusted to maintain a constant voltage across the sense resistor while the timing capacitor starts to charge. if the timer voltage ever exceeds 4.65v, gate is pulled low. gate is also pulled to gnd whenever uv is pulled low, the v cc supply voltage drops below the externally programmed undervoltage threshold, or v cc drops below the internal uvlo threshold (9.8v). gate is clamped internally to a maximum voltage of 11.6v (typ) above v cc under normal operating conditions. driv- ing this pin beyond the clamp voltage may damage the part. a zener diode is needed between the gate and source of the external mosfet to protect its gate oxide under instantaneous short-circuit conditions. see applications information. sense (pin 7): current limit sense input. a sense resistor is placed in the supply path between v cc and sense. the current limit circuit regulates the voltage across the sense resistor (v cc C sense) to 55mv while in current limit when fb is 2v or higher. if fb drops below 2v, the regulated voltage across the sense resistor de- creases linearly to 14mv when fb is 0v. to defeat current limit, connect sense to v cc . v cc (pin 8): input supply voltage. the positive supply input ranges from 10.8v to 80v for normal operation. i cc is typically 1.8ma. an internal circuit disables the lt4256-1/lt4256-2 for inputs less than 9.8v (typ).
lt4256-1/lt4256-2 7 425612fa block diagra w + C C + C + 108 a v p v p logic 2v 14mv ~ 55mv 9.8v 4v v cc internal uv timer low timer high gnd 0.65v 4.65v C + C + 3.99v 3.99v pwrgd timer 4256 bd v cc sense v p gen fb 3 a uv gate + C + C charge pump and gate driver ref gen 8 7 6 3 5 4 current limit foldback 2 1 uv
lt4256-1/lt4256-2 8 425612fa test circuit ti i g diagra s w u w figure 2. uv to gate timing figure 3. v out to pwrgd timing figure 4. sense to gate timing figure 1 v cc gate sense timer pwrgd fb uv 48v 48k gnd 4256 f01 100pf + C uv 4256 f02 gate v out +2v t plhuv 4v v out +2v t phluv 3.6v v cc C sense 4256 f04 gate v cc t phlsense 55mv applicatio s i for atio wu u u hot circuit insertion when circuit boards are inserted into a live backplane, the supply bypass capacitors on the boards draw high peak currents from the backplane power bus as they charge. the transient currents can permanently damage the con- nector pins and glitch the system supply, causing other boards in the system to reset. the lt4256-1/lt4256-2 are designed to turn on a boards supply voltage in a controlled manner, allowing the board to be safely inserted or removed from a live backplane. the device also provides undervoltage as well as overcurrent protection while a power good output signal indicates when the output supply voltage is ready with a high output. power-up sequence an external n-channel mosfet pass transistor (q1) is placed in the power path to control the power up of the supply voltage (figure 5). resistor r5 provides current detection and capacitor c1 controls the gate slew rate. resistor r7 compensates the current control loop while r6 prevents high frequency oscillations in q1. fb 4256 f03 pwrgd 1v t plhfb 4.45v 1v t phlfb 3.99v
lt4256-1/lt4256-2 9 425612fa applicatio s i for atio wu u u figure 5. 1600ma, 48v application figure 6. start-up waveforms when the power pins first make contact, transistor q1 is held off. if the voltage on v cc is above the externally programmed undervoltage threshold, v cc is above 9.8v, and the voltage on timer is less than 4.65v (typ), transis- tor q1 will be turned on (figure 6). the voltage on gate rises with a slope equal to 32 a/c1 and the supply inrush current is set at: i inrush = c l ? 32 a/c1 (1) where c l is the total load capacitance. to reduce inrush current, increase c1 or decrease load capacitance. if the voltage across the current sense resis- tor r5 reaches v sensetrip , the inrush current will be limited by the internal current limit circuitry. the voltage on gate is adjusted to maintain a constant voltage across the sense resistor and timer begins to charge. when the fb voltage goes above the low-to-high v fb threshold, pwrgd goes high. undervoltage detection the lt4256-1/lt4256-2 uses uv to monitor the v cc voltage to determine when it is safe to turn on the load and allow the user the greatest flexibility for setting the thresh- old. any time that uv goes below 3.6v, gate will be pulled low until uv goes above 4v again. the uv threshold should never be set below the internal uvlo threshold (9.8v typically) because the benefit of uvs hysteresis will be lost, making the lt4256-1/ 4256 f05 r5 0.025 ? lt4256-1/ lt4256-2 sense 6 2 3 4 87 1 5 v cc gate fb pwrgd uv timer gnd v in 48v gnd (short pin) q1 irf530 d1 cmpz5241b 11v r2 8.06k r1 64.9k r7 100 ? r9 4.02k r6 10 ? r8 36.5k pwrgd v out 48v 1.6a r4 27k c l c2 33nf c3 0.1 f c1 10nf d2 smat70a uv = 36v pwrgd = 40v + lt4256-2 more susceptible to noise (v cc must be at least 9.8v when uv is at its 3.6v threshold). uv is filtered with c3 to prevent noise spikes and capacitively coupled glitches from shutting down the lt4256-1/lt4256-2 output erroneously. to calculate the uv threshold, use the following equations: rr v v krr k v r r thuvlh thuvlh 12 4 1 20 1 2 200 36 1 1 2 = ? ? ? ? ? ? ? ? + ? =+ ? ? ? ? ? ? (2) (3) (4) . where v thuvlh is the desired uv threshold voltage when v cc is rising (l-h), etc. i out 500ma/div v out 50v/div 5ms/div 4256 f06 pwrgd 50v/div gate 50v/div c l = 125 f
lt4256-1/lt4256-2 10 425612fa applicatio s i for atio wu u u figure 7. current limit sense voltage vs feedback pin voltage figure 8. response time to overcurrent figure 11 shows how the lt4256-1/lt4256-2 are com- manded to shut off with a logic signal. this is accom- plished by pulling the gate of the open-drain mosfet, q2, (tied to the uv pin) high. short-circuit protection the lt4256-1/lt4256-2 features a programmable foldback current limit with an electronic circuit breaker that protects against short circuits or excessive load currents. the current limit is set by placing a sense resistor (r5) between v cc and sense. the current limit threshold is calculated as: i limit = 55mv/r5 (5) where r5 is the sense resistor. to limit excessive power dissipation in the pass transistor and to reduce voltage spikes on the input supply during short-circuit conditions at the output, the current folds back as a function of the output voltage, which is sensed internally on fb. if the lt4256-1/lt4256-2 go into current limit when the voltage on fb is 0v, the current limit circuit drives the gate pin to force a constant 14mv drop across the sense resistor. as the output at fb increases, the voltage across the sense resistor increases until the fb pin reaches 2v, at which point the voltage across the sense resistor is held constant at 55mv (see figure 7). for a 0.025 ? sense resistor, the current limit is set at 2200ma and folds back to 560ma when the output is shorted to ground. thus, mosfet peak power dissipation under short-circuit conditions is reduced from 105.6w to 26.5w. see the layout considerations section for impor- tant information about board layout to minimize current limit threshold error. the lt4256-1/lt4256-2 also features a variable overcurrent response time. the time required for the part to regulate the gate voltage is a function of the voltage across the sense resistor connected between v cc and sense. this helps to eliminate sensitivity to current spikes and transients that might otherwise unnecessarily trigger a current limit response and increase mosfet dissipation. figure 8 shows the response time as a func- tion of the overdrive at sense. timer timer provides a method for programming the maximum time the part is allowed to operate in current limit. when the current limit circuitry is not active, the timer pin is pulled to gnd by a 3 a current source. when the current limit circuitry becomes active, a 108 a pull-up current source is connected to timer and the voltage will rise with a slope equal to 105 a/c timer as long as the circuitry stays active. once the desired maximum current limit time is known, the capacitor value is: c nf t ms c a v t [] ?[ ]; . ? == 25 105 465 (6) 14mv 0v 2v fb 4256 f07 55mv v cc C v sense 50 100 150 200 4256 f08 12 10 8 6 4 2 response time ( s) v cc C v sense (mv) 0
lt4256-1/lt4256-2 11 425612fa applicatio s i for atio wu u u when the timer pin reaches 4.65v (typ), the internal fault latch is set causing gate to be pulled low and timer to be discharged to gnd by the 3 a current source. the part is not allowed to turn on again until the voltage on timer falls below 0.65v (typ). timer must never be pulled high by a low impedance because whenever timer rises above the upper threshold (typically 4.65v) the pin characteristics change from a high impedance current source to a low impedance. whenever gate is commanded off by any fault condition, it is discharged rapidly, turning off the external mosfet. the waveform in figure 9 shows how the output latches off following a current fault (lt4256-1). the drop across the sense resistor is held at 55mv as the timer ramps up. once timer reaches its shutdown threshold (4.65v typically), the circuit latches off. the lt4256-1 latches off after a current limit fault. after the lt4256-1 latches off, the part may be commanded to start back up. this is accomplished by cycling uv to ground and then back high (this command can only be accepted after timer discharges back below the 0.65v typical threshold, to prevent overheating transistor q1). automatic restart the lt4256-2 will automatically restart after an overcurrent fault. these waveforms are shown in figure 10. the lt4256-2 functionality is as follows: when an overcurrent condition occurs, the gate pin is servoed to maintain a constant voltage across the sense resistor, and the capacitor c2 at the timer pin will begin to charge. when the voltage at the timer pin reaches 4.65v (typ), the gate pin is pulled low. when the voltage at the timer pin ramps back down to 0.65v (typ), the lt4256-2 turns on again. if the short-circuit condition at the output still exists, the cycle will repeat itself indefinitely. the duty cycle under short-circuit conditions is 3% which prevents q1 from overheating. figure 9. lt4256-1 current limit waveforms figure 10. lt4256-2 current limit waveforms 10ms/div 4256 f09 i out 500ma/div v out 50v/div timer 5v/div gate 50v/div i out 500ma/div v out 50v/div timer 5v/div gate 50v/div 10ms/div 4256 f10
lt4256-1/lt4256-2 12 425612fa applicatio s i for atio wu u u figure 12. active low enable pwrgd application 4256 f11 r5 100m ? lt4256-1/ lt4256-2 sense 6 2 3 4 87 1 5 v cc gate fb pwrgd uv timer gnd v in (short pin) q1 irf530 d1 cmpz5241b 11v r2 8.06k r1 64.9k r7 100 ? r6 10 ? v out v logic r4 27k r8 36.5k c l r10 27k c2 33nf c3 0.1 f c1 10nf r9 4.02k q2 2n3904 pwrgd gnd d2 smat70a uv = 36v pwrgd = 40v power good detection the lt4256-1/lt4256-2 includes a comparator for moni- toring the output voltage. the output voltage is sensed through the fb pin via an external resistor string. the comparators output (pwrgd) is an open collector ca- pable of operating from a pull-up as high as 80v. pwrgd can be used to directly enable/disable a power module with an active high enable input. figure 12 shows how to use pwrgd to control an active low enable input power module. signal inversion is accomplished by tran- sistor q2 and r10. 4256 f07 r5 0.010 ? lt4256-1/ lt4256-2 sense 6 3 4 7 8 1 5 v cc gate fb 2 pwrgd uv timer gnd v in 48v (short pin) q1 irf530 d1 cmpz5241b 11v r2 8.06k q2 vn2222 r1 64.9k r7 100 ? r9 4.02k r6 10 ? r8 36.5k v out 48v 4a r4 51k c l c2 33nf c3 0.01 f off signal from mpu c1 10nf gnd d2 smat70a uv = 36v pwrgd = 40v figure 11. how to use a logic signal to control lt4256 turn-on/-off the thresholds for the fb pin are 4.45v (low to high) and 3.99v (high to low). to calculate the pwrgd thresholds, use the following equations: r v krr k v 8= v ? r9, high to low (7) (8a) = 4.45v 1+ r8 r9 , low to high (8b) thpwrgd thpwrgd 399 1 20 8 9 200 . C ? ? ? ? ? ? ? + ? ? ? ? ? ? ?
lt4256-1/lt4256-2 13 425612fa figure 13. ? v gate vs v cc supply transient protection the lt4256-1/lt4256-2 is 100% tested and guaranteed to be safe from damage with supply voltages up to 80v. however, voltage transients above 100v may cause per- manent damage. during a short-circuit condition, the large change in currents flowing through the power supply traces can cause inductive voltage transients which could exceed 100v. to minimize the voltage transients, the power trace parasitic inductance should be minimized by using wider traces or heavier trace plating and a 0.1 f bypass capacitor should be placed between v cc and gnd. a surge suppressor, as shown in the application diagrams, (transzorb) at the input can also prevent damage from voltage transients. gate pin a curve of gate drive vs v cc is shown in figure 13. gate is clamped to a maximum voltage of 12.8v above v cc . this clamp is designed to sink the internal charge pump cur- rent. an external zener diode must be used as shown in all applications. at a minimum input supply voltage of 12v, the minimum gate drive voltage is 4.5v. when the input supply voltage is higher than 20v, the gate drive voltage is at least 10v and a standard threshold mosfet can be used. in applications from 12v to 15v range, a logic level mosfet must be used. in some applications it may be possible for the v out pin to ring below ground (due to the parasitic trace inductance). v cc (v) 10 ? v gate (v) 8 9 10 4256 f13 7 6 5 20 30 70 60 50 40 80 12 11 applicatio s i for atio wu u u higher current applications, especially where the output load is physically far away from the lt4256-1/lt4256-2 will be more susceptible to these transients. this is normal and the lt4256-1/lt4256-2 have been designed to allow for some ringing below ground. however, if the applica- tion is such that v out can ring more than 10v below ground, damage may occur to the lt4256-1 and an external diode from ground (anode) to v out (cathode) must be added to the circuit as shown in figure 14 (it is critical that the reverse breakdown voltage of the diode be higher than the highest expected v cc voltage). a capacitor placed from ground to v out directly at the lt4256-1/ lt4256-2 can help reduce the amount of ringing on v out but it may not be enough for some applications. during a fault condition, the lt4256-1/lt4256-2 pulls down on gate with a switch capable of sinking about 60ma. once gate drops below the output voltage by a diode forward voltage, the external zener will forward bias and v out will also be discharged to gnd. in addition to the gate capacitance, the output capacitance will be dis- charged through the lt4256-1/lt4256-2. in applications utilizing very large external n-channel mosfets, the possibility exists for the mosfet to turn on when initially inserted into a live backplane (before the lt4256-1/lt4256-2 becomes active and pulls down on gate). this is due to the drain to gate capacitance forcing current into r7 and c1 when the drain voltage steps up from ground to v in with an extremely fast rise time. to alleviate this situation, a diode, d3, should be put across r7 with the cathode connected to c1 as shown in figure 15.
lt4256-1/lt4256-2 14 425612fa applicatio s i for atio wu u u figure 14. negative output voltage protection diode application 4256 f14 r5 0.033 ? lt4256-1/ lt4256-2 sense 6 2 3 4 87 1 5 v cc gate fb pwrgd uv timer gnd v in (short pin) q1 irf530 d1 cmpz5241b 11v r2 8.06k r1 64.9k r7 100 ? r9 4.02k r6 10 ? r8 36.5k v out r4 27k c l 100 f c2 33nf c3 0.1 f c1 10nf gnd d2 smat70a d3 mra4003t3 uv = 36v pwrgd = 40v notes on using the lt4256 in lt1641 applications even though the lt4256 and lt1641 have the same pinout, several changes were made to improve overall system accuracy and increase noise immunity. these changes are spelled out in table 1 and must be accounted for if using the lt4256 in an lt1641 application. layout considerations to achieve accurate current sensing, a kelvin connection to the current sense resistor (r5 in typical application circuit) is recommended. the minimum trace width for 1oz copper foil is 0.02" per amp to make sure the trace stays at a reasonable temperature. 0.03" per amp or wider is recommended. note that 1oz copper exhibits a sheet resistance of about 530 ? / ? . small resistances can cause large errors in high current applications. noise immunity will be improved significantly by locating resis- tor dividers close to the pins with short v cc and gnd traces. a 0.1 f decoupling capacitor from uv to gnd is also required. table 1. differences between lt1641 and lt4256 specification lt1641 lt4256 comments uv threshold 1.313v 4v higher 1% reference for better noise immunity and system accuracy fb threshold 1.233v 3.99v higher 1% reference for better noise immunity and system accuracy timer current 70% 40% more accurate timeout timer shutdown v 1.233v 4.65v higher trip voltage for better noise immunity gate i pu 10 a30 a higher current to accommodate higher leakage mosfets or parallel devices gate resistor 1k ? 100 ? different compensation for current limit loop foldback i lim 12mv 14mv slightly different current limit trip point i lim threshold 47mv 55mv slightly different current limit trip point fault latch reset 1.233v 0.85v better noise immunity threshold voltage
lt4256-1/lt4256-2 15 425612fa u package descriptio s8 package 8-lead plastic small outline (narrow .150 inch) (reference ltc dwg # 05-08-1610) .016 C .050 (0.406 C 1.270) .010 C .020 (0.254 C 0.508) 45 0 C 8 typ .008 C .010 (0.203 C 0.254) so8 0303 .053 C .069 (1.346 C 1.752) .014 C .019 (0.355 C 0.483) typ .004 C .010 (0.101 C 0.254) .050 (1.270) bsc 1 2 3 4 .150 C .157 (3.810 C 3.988) note 3 8 7 6 5 .189 C .197 (4.801 C 5.004) note 3 .228 C .244 (5.791 C 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
lt4256-1/lt4256-2 16 425612fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com related parts part number description comments lt1641-1/lt1641-2 positive 48v hot swap controller in so-8 9v to 80v operation, active current limit, autoretry/latchoff ltc4211 single hot swap controller with multifunction current control 2.5v to 16.5v, active inrush limiting, dual level cicuit br eaker ltc4251 C 48v hot swap controller in sot-23 floating supply from C15v, active current limiting, fast circuit breaker ltc4252-1/ltc4252-2 C 48v hot swap controller in msop floating supply from C15v, active current limiting, power good output ltc4253 C 48v hot swap controller and supply sequencer floating supply from C15v, active current limiting, enables three dc/dc converters lt4254 positive high voltage hot swap controller 10.8v to 36v, open-circuit detection ? linear technology corporation 2004 lt/lwi/lt 0705 rev a ? printed in usa applicatio s i for atio wu u u figure 15. high dv/dt mosfet turn-on protection circuit 4256 ta03 r5 0.033 ? lt4256-1/ lt4256-2 sense 6 2 3 4 87 1 5 v cc gate fb pwrgd uv timer gnd v in (short pin) q1 irf530 d1 cmpz5241b 11v r2 8.06k r1 64.9k r7 100 ? r9 4.02k r6 10 ? r8 36.5k v out r4 27k c l 100 f c2 33nf c3 0.1 f c1 10nf gnd d2 smat70a d3 1n4148w uv = 36v pwrgd = 40v

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